1. Field of the Invention
The invention relates generally to circuit design. More particularly, this invention relates to a technique for reducing I/O supply noise.
2. Background Art
In electronic circuits, an input/output (xe2x80x9cI/Oxe2x80x9d) supply can be shown as an equivalent circuit 10 as shown in FIG. 1. A typical I/O supply generates and receives high and low data bits dependent on inputs to one or more transceiver devices within the I/O supply. Specifically, the equivalent circuit 10 includes a power supply source 12, a supply resistance (Rs) 14, a supply inductance (Ls) 16, and transceiver circuits 18 and 19. Each of these system components 12, 14, 16, 18, and 19 represent an equivalent value of all of the combined respective components in the I/O supply. The performance of the circuit 10 is frequency dependent. As shown in the graph of FIG. 2, as the frequency of the system increases, the impedance of the circuit increases as well. This increase in impedance 24 continues until a peak 20 is reached at a resonance frequency. Finally, the impedance will subside at even higher frequencies.
The rate of increase in the impedance of the circuit as the frequency approaches its resonance value is quantified as a xe2x80x9cQxe2x80x9d value. The xe2x80x9cQxe2x80x9d value is calculated as Q=((L/C))/R; where L is the system inductance value; where C is the system capacitance value; and where R is the system resistance value. As shown in FIG. 2, under normal operations, the equivalent circuit 10 has a very high Q value 24 near the resonance frequency. A high current transient within the high Q region of the frequency band causes significant noise in the I/O supply system. Supply noise can result in such problems as voltage variation, signal jitter, signal stability, component or logic malfunction, signal interference, etc. For instance, a logic device operatively connected to the I/O supply will have more jitter in the presence of I/O supply noise, which effectively leads to a reduction in the speed at which an integrated circuit can operate. Further, Voltage variation is a significant problem because the indeterministic distribution of power to system components can lead to a loss of system performance.
It would be advantageous to decrease the Q value of the I/O supply system and thereby reduce I/O supply noise. A reduced Q value 26 is also shown in FIG. 2. This Q value 26 would have the advantage of substantially reducing the noise of the respective system. FIG. 3 shows a prior art method of reducing the Q value for an I/O supply system 32. The prior art method used in FIG. 3 involves inserting a de-coupling capacitor 34 across the power supply of the I/O supply 32 in order to increase the system capacitance. However, the capacitor 34 takes up a significant amount of space on the chip.
Another phenomenon inherent in the design of a typical I/O supply system is inefficient signal current flow. FIG. 4a shows the flow of current when the I/O supply system 10 is driving a high value. In driving a high value to a transmission line 33, the I/O supply system 10 actually sinks some current in addition to sourcing enough current to drive the transmission line 33 high. As shown by the dotted arrow line in FIG. 4a, the sunk current from the transmission line 33 must flow around the I/O supply system 10. Typically, current flow in such a manner faces high impedance, especially when current has to flow through a voltage source 12, as shown in FIG. 4a. Thus, current flow in the typical I/O supply system 10 experiences high impedance, a performance degrading effect.
FIG. 4b shows the flow of current from the transmission line 33 when the I/O supply system 32 has a capacitor 34 positioned across the I/O power supply 12. In this case, current from the transmission line 33 flows through the equivalent circuit of the I/O supply system 12 and the capacitor loop as shown in FIG. 4b. This phenomenon also results in non-optimal performance in that a significant portion of the current flowing from the transmission line 33 into the I/O supply system 12 still experiences high impedance.
Thus, there is a need for an I/O supply system that provides a low impedance current flow path, effectively leading to performance improvement. Further, there is a need for a space efficient method of reducing voltage variation for a I/O supply system.
According to one aspect of the present invention, a method for reducing noise in an I/O supply comprises supplying current to an I/O supply output from a power supply and connecting a shunting device in parallel with the power supply of the I/O supply, where a portion of the current supplied to the I/O supply output flows through the shunting device.
According to another aspect, an I/O supply comprises a power supply, an I/O output selectively driven by the power supply, and a shunting device connected in parallel with the power supply.
According to another aspect, an apparatus for reducing noise in an I/O supply comprises means for supplying current to an I/O supply output from a power supply and means for connecting a shunting device in parallel with the power supply of the I/O supply, where a portion of the current supplied to the I/O supply output flows through the shunting device.
Other aspects and advantages of the invention will be apparent from the following description and the appended claims.